Intended format

Prompt the model to reason briefly, then emit final Verilog between tags:

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Thinking:
[BEGIN]
module TopModule(...);
  ...
endmodule
[DONE]

Use code inside [BEGIN] / [DONE] as final artifact.

Evaluation in this project

Local VerilogEval v2 spec-to-RTL direct single-adapter eval, no retry, no selector, no compiler feedback before final answer:

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v33 max4096: compile 113/156, pass 80/156 = 51.3%
v33 max1024: compile 101/156, pass 76/156 = 48.7%

These are clean direct adapter results, not agentic pipeline results. The project best practical pipeline remains a separate verifier-selector system.

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python
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from transformers import AutoModelForCausalLM, AutoTokenizer
from peft import PeftModel

base = "Qwen/Qwen3.5-9B"
adapter = "Pablo-Flores-Mollinedo/verilog-qwen3.5-9b-v33-thinking-reinforced-lora"

tok = AutoTokenizer.from_pretrained(adapter, trust_remote_code=True)
model = AutoModelForCausalLM.from_pretrained(base, trust_remote_code=True, device_map="auto")
model = PeftModel.from_pretrained(model, adapter)

Notes

• Adapter only; requires the base model license/weights.
• Generated RTL should be compiled and simulated before use.
• Benchmark scores are finite-testbench simulation results, not formal proof.